Analyzing Trade-offs in Scan Power and Test Data Compression for Systems-on-a-Chip

This paper investigates the relationship between test data compression and power dissipation during scan testing. It is shown how combining a recently proposed symmetric coding scheme and a new weighted scan latch reordering (W-SLR) algorithm, leads to efficient exploration in the scan power and test data compression solution space. This is achieved by reducing and, at the same time, balancing the transition activity in scan-in and scan-out sequences. This will impact, on the one hand, the test data compression which depends only on the scan-in sequence, and, on the other hand, the overall scan power dissipation which depends on both the scan-in and the scan-out sequences. Trade-off analysis using ISCAS89 benchmark circuits shows that, by employing the recently proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can easily and explicitly control the scan power and volume of test data.